Next_state if(sequence_in = '0') then - "100" Next_state if(sequence_in = '0') then - "10" Signal current_state, next_state : MOORE_FSM īegin - Sequential memory of the VHDL MOORE FSM Sequence Detector process(clock,reset)Ĭurrent_state if(sequence_in = '1') then - "1" Sequence_in : in std_logic - binary sequence inputĭetector_out : out std_logic - output of the VHDL sequence detectorĪrchitecture Behavioral of VHDL_MOORE_FSM_Sequence_Detector is type MOORE_FSM is (Zero, One, OneZero, OneZeroZero, OneZeroZeroOne) : FPGA projects, Verilog projects, VHDL projects - VHDL project: VHDL code for Sequence Detector using Moore FSM - The sequence being detected is "1001" or One Zero Zero One library IEEE Įntity VHDL_MOORE_FSM_Sequence_Detector is port (
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